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Hyderabad, 3-5 years: The Engineer will be responsible for execution of block level physical design activities for a given ASIC product.

Hyderabad, 4-6 years: The position is for a Senior Physical Design Engineer in the AMD PSE PD group catering to building the next generation fusion SoCs.

Hyderabad, 4-7 years: Develop and document detailed test plans, block and system-level test benches and reference models

Hyderabad, 4-8 years: some full chip activities covering floor planning, clocking, budgeting, timing, verification etc.,

Hyderabad, 3-5 years: The Engineer will be responsible for execution of block level physical design activities for a given ASIC product.

Hyderabad, 6-10 years: The position is for a PD staff engineer in the AMD PSE PD group catering to building the next generation fusion SoCs.

Hyderabad, 4-6 years: The position is for a Senior Physical Design Engineer in the AMD PSE PD group catering to building the next generation fusion SoCs.

Hyderabad, 5-8 years: The candidate will be responsible for participating in the pre-silicon block and system level design for Integrated Graphics chipsets.

Hyderabad, 3-6 years: The Engineer will be responsible for execution of block level physical design activities for a given ASIC product.

Hyderabad, 4-8 years: some full chip activities covering floor planning, clocking, budgeting, timing, verification etc.,

Hyderabad, 4-8 years: some full chip activities covering floor planning, clocking, budgeting, timing, verification etc.,

Hyderabad, 6-8 years: The candidate will technically lead and mentor a team of engineers on Physical Design (place and route ) duties both on block.

Hyderabad, 4-7 years: As a leader in the semiconductor industry, AMD has a truly global profile. We build our products on three continents, and we maintain offices in dozens of cities scattered all over the world.We invite you to consider AMD.

Hyderabad, 4-6 years: The position is for a Senior Physical Design Engineer in the AMD PSE PD group catering to building the next generation fusion SoCs.

Hyderabad, 3-6 years: The Engineer will be responsible for execution of block level physical design activities for a given ASIC product.

Hyderabad, 4-8 years: some full chip activities covering floor planning, clocking, budgeting, timing, verification etc.,

Hyderabad, 4-6 years: The position is for a Senior Physical Design Engineer in the AMD PSE PD group catering to building the next generation fusion SoCs.

Hyderabad, 4-6 years: The position is for a Senior Physical Design Engineer in the AMD PSE PD group catering to building the next generation fusion SoCs.

Hyderabad, 4-6 years: The position is for a Senior Physical Design Engineer in the AMD PSE PD group catering to building the next generation fusion SoCs.

Hyderabad, 3-6 years: The Engineer will be responsible for execution of block level physical design activities for a given ASIC product.

Hyderabad, 0-3 years: The Candidate should have a MS/BS/Diploma with 0 to 3 years of experience in complex analog/digital layout design, with an aptitude to learn and make a career in the area of VLSI layout design.

Hyderabad, 4-6 years: The position is for a Senior Physical Design Engineer in the AMD PSE PD group catering to building the next generation fusion SoCs.

Hyderabad, 4-6 years: The position is for a Senior Physical Design Engineer in the AMD PSE PD group catering to building the next generation fusion SoCs.

Hyderabad, 3-6 years: The Engineer will be responsible for execution of block level physical design activities for a given ASIC product.

Hyderabad, 3-5 years: The Engineer will be responsible for execution of block level physical design activities for a given ASIC product.

Hyderabad, 3-5 years: The Engineer will be responsible for execution of block level physical design activities for a given ASIC product.

Hyderabad, 6-10 years: The position is for a PD staff engineer in the AMD PSE PD group catering to building the next generation fusion SoCs.

Hyderabad, 4-6 years: The position is for a Senior Physical Design Engineer in the AMD PSE PD group catering to building the next generation fusion SoCs.

Hyderabad, 4-8 years: Develop and document detailed test plans, block and system-level test benches and reference models.

Hyderabad, 3-6 years: The Engineer will be responsible for execution of block level physical design activities for a given ASIC product.

Hyderabad, 3-6 years: The Engineer will be responsible for execution of block level physical design activities for a given ASIC product.

Hyderabad, 4-8 years: some full chip activities covering floor planning, clocking, budgeting, timing, verification etc.,

Hyderabad, 4-6 years: The position is for a Senior Physical Design Engineer in the AMD PSE PD group catering to building the next generation fusion SoCs.

Hyderabad, 4-8 years: some full chip activities covering floor planning, clocking, budgeting, timing, verification etc.,

Hyderabad, 4-8 years: some full chip activities covering floor planning, clocking, budgeting, timing, verification etc.,

Hyderabad, 6-8 years: The candidate will technically lead and mentor a team of engineers on Physical Design (place and route ) duties both on block.

Hyderabad, 3-5 years: The Engineer will be responsible for execution of block level physical design activities for a given ASIC product.

Hyderabad, 6-10 years: The position is for a PD staff engineer in the AMD PSE PD group catering to building the next generation fusion SoCs.

Hyderabad, 4-8 years: some full chip activities covering floor planning, clocking, budgeting, timing, verification etc.,

Hyderabad, 3-5 years: The Engineer will be responsible for execution of block level physical design activities for a given ASIC product.

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